Conventionally, in a manufacturing process of a semiconductor memory, there is a method of specifying a location of a fail bit (failed memory cell) by using a fail bit map (FBM) of the semiconductor memory. For displaying the FBM, first, an electrical test result for each memory cell of the semiconductor memory is detected by using a tester. Then, typically, one-dimensional array information (logical FBM address) corresponding to an order of collecting the electrical test results by the tester is converted into two-dimensional coordinate values (physical FBM address) associated with a physical layout of the memory cells of the semiconductor memory on a wafer, thereby displaying positional information on the failed memory cell determined by the electrical test results on a display device (see Japanese Patent No. 3256555).
Moreover, there is a technology in which the electrical test results output from the tester are divided into a plurality of pieces and the physical position of the fail bit is specified from each divided piece of the electrical test results based on a definition table in which the logical FBM address and the physical FBM address of the electrical test results are associated with each other for each divided piece of the electrical test results (see Japanese Patent Application Laid-open No. 2001-324546).
Recently, increase in capacity of the semiconductor memory has progressed at a very rapid pace. For example, in a NAND flash memory, products having a storage capacity of tens of gigabits have already been mass produced, and the storage capacity has been increasing to reach terabit in a few years. In the above two technologies, a calculation cost proportional to the number of the memory cells is required, so that a processing time for generating the FBM increases with the increase of the storage capacity of a memory of a target product. The increased processing time for generating the FBM means that the time of a failure analysis becomes long. In other words, acceleration of the process of generating the FBM is an urgent need for coping with a large-capacity semiconductor memory.